Silicon Implementation of SHA-3 Finalists: BLAKE, Grøstl, JH, Keccak and Skein

Hardware implementation quality is an important factor in selecting the NIST SHA-3 competition finalists. However, a comprehensive methodology to benchmark five final round SHA-3 candidates in ASIC is challenging. Many factors need to be considered, including application scenarios, target technologies and optimization goals. This work describes detailed steps in the silicon implementation of a SHA-3 ASIC. The plan of ASIC prototyping with all the SHA-3 finalists, as an integral part of our SHA-3 ASIC evaluation project, is motivated by our previously proposed methodology, which defines a consistent and systematic approach to move a SHA-3 hardware benchmark process from FPGA prototyping to ASIC implementation. We have designed the remaining five SHA-3 candidates in 0.13 μm IBM process using standard-cell CMOS technology. The fabricated chip is due from foundry in May 2011. In this submission, we discuss our proposed methodology for SHA-3 ASIC evaluation and report the latest results based on pre-silicon post-layout simulation of the five SHA-3 finalists with Round 3 tweaks.